LOGIC OPERATIONS AND TRUTH TABLES. Digital logic circuits handle data encoded in binary form, i.e. signals that have only two values, 0 and 1. Binary logic. Digital Logic Design. B i. ▫ Basics. ▫ Combinational Circuits. ▫ Sequential Circuits. Pu-Jen Cheng. Adapted from the slides prepared by S. Dandamudi for the. Digital Logic Design. ENGG 1st Semester, Dr. Kenneth Wong. Department of Electrical and. Electronic Engineering.
|Language:||English, Spanish, French|
|Genre:||Academic & Education|
|ePub File Size:||22.80 MB|
|PDF File Size:||11.43 MB|
|Distribution:||Free* [*Regsitration Required]|
Digital Logic is the basis of electronic systems, such as computers and cell Digital Logic Design is foundational to the fields of electrical engineering and. This material has been developed for the first course in Digital Logic Design. The content is Digital Design Overview (from Transistor to Super Computer). PDF Drive is your search engine for PDF files. As of today we have 78,, eBooks for you to download for free. No annoying ads, no download limits, enjoy .
Draw the resulting circuit diagram from the equation give above: Download pdf. Share this article with your classmates and friends so that they can also follow Latest Study Materials and Notes on Engineering Subjects. Each multiplexer selects half of the data inputs. This latch has only two inputs: Procedural, which is used for circuits with storage, or as a convenient way to write conditional logic. Y 0 1 Simplified functions:
K-maps for A0 and A1 Logic Circuit: Notice that 4-to-2 Priority Encoder is simpler than 4-to-2 Encoder because the function of the V signal is simpler.
Output depends on the of the data input lines. It has 3 variables, therefore we can implement it with 8-to-1 MUX. Consider an arbitrary function F X1,X2,…,Xn: It has 3 variables. Each multiplexer selects half of the data inputs. Construct a logic circuit that selects between 2 sets of 4-bit inputs see next slide for solution.
Demultiplexers cont. Left- edge cells are adjacent to right-edge cells. Top cells are adjacent to bottom cells. Left-edge cells are adjacent to right-edge cells. They are identical!
Boolean functions? Simpler Boolean function can mean cheaper, smaller, faster circuit more details later. The number of cells in a group must be a power of 2 2, 4, 8, …. The result after the simplification may not be unique. Simplifying a Boolean Function using 2-variable K-map examples Given functions: Y 0 1 Simplified functions: Simplified functions: Given function: The K-map of a Boolean function Obtain: The simplest SOP expression for the function 1.
Find all primary implicants PIs of the function. Select all essential PIs. For remaining minterms not included in the essential PIs, select a set of other PIs to cover them, with minimal overlap in the set. The resulting simplified function is the logical OR of the product terms selected above.
Each x may be arbitrarily assigned the value 0 or 1 in an implementation. F1 and F2 are algebraically not equal.
The Duality Principle cont. With respect to duality, Identities 1 — 8 and Properties 10 — 17 have the following relationship: A variable or its complement Example: How many columns are there in the truth table of F x1,x2,…,xN-1,xN? How many rows are there in the truth table of F x1,x2,…,xN-1,xN? Truth Table cont. This motivates the use of other representations. To introduce them we need the following definitions: A variable or its complement.
Variable Y in m5 is complemented because its value in b5 is 0. Variables X and Y in M5 are complemented because their values in b5 are 1. The number of transistors determines the Level of Integration: Perform basic digital functions, e. Implement digital systems, e.
Implements complex digital systems, e. There are two types of number systems: The hundreds, tens, units, and tenths are powers of 10 implied by the position of the digits.
These systems have a more compact representation of binary quantities. Converting the fraction part 0. The convention is to make the sign bit 0 for positive numbers and 1 for negative numbers. We can discard it, leaving the correct result M — N. A carry out of the sign bit position is discarded.
The difference M - N can be obtained as follows: However, the advantages of using BCD are: Other Useful Decimal Codes: For more examples and detailed description of the material in the lecture notes, please refer to the main textbook: Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in the circuit.
Inputs Outputs Combinational Circuit Memory Element - Sequential circuits can be categorized as being synchronous or asynchronous.
Lecture Notes Prepared by Amir G. This means that the output of the top gate Q is 1, as both of its inputs are 0. This is called the set state. Then the output of the top gate Q is definitely 1 note that the output of a NAND gate is 1 if at least one of its inputs is 0.
Positive-edge response Negative-edge response - Two different ways to construct a D flip-flop from latches are shown below. JK Flip-Flop: Implement the circuits and verify the results. Equipment Used: This is done in the D Latch. This latch has only two inputs: Truth Table for D latch: Draw the circuit for D Latch. Figure 9. D-Flipflop IC Theory: The D flipflop is almost the same as the SR flipflop but with a difference that it has only two input, D data and C clock.
Fill in the truth table for D Flipflop. Trainer, 74LS76 JK flipflop , basic gates. The basic concept in the implementation if the state machine is that we should know about the truth table, excitation table of the JK flipflop and transition table. This lab contains almost all the concepts that have been taught during the DLD course.
Following is the state machine that must be implemented. Truth Table for JK flip flop: Fill in the following transition table P. Fill in the following K-Maps for the following outputs JB: Write the equations derived from the K-Maps. Fill in the following Blanks.
Circuit Diagram: Draw the resulting circuit diagram from the equation give above: Understand Basics of Verilog. It provides the designer entry into the world of large, complex digital systems design. The Verilog language provides the digital system designer with a means of describing a digital system at a wide range of levels of abstraction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels.
It also fulfils the need for verifying the design for functionality and timing constraints like propagation delay setup and hold times.
The components of the target design can be described at different levels with the help of constructs in Verilog. Circuit Level: MOS switch is the basic element which can be used to build basic circuits like inverters, logic gates, 1-bit dynamic and static memories.
Gate Level or structural level: Design is carried out in terms of basic gates. Primitives can be incorporated into design descriptions directly.
Data Flow Level: All possible operations on signals and variables are represented in terms of assignments. Behavioral Level: This level describes a system by concurrent algorithms and the design description looks like a C program.
Compactness and the comprehensive nature of the design description make the development process fast and efficient. Functions, Tasks and Always blocks are the main elements. There are two types of code in most HDLs: Structural, this is a verbal wiring diagram without storage.
Changing t will change p. Procedural, which is used for circuits with storage, or as a convenient way to write conditional logic. Keywords The keywords define the language constructs. All keywords in Verilog are in small letters and require to be used as such. Some of the examples are: Numbers The numbers can be of integer type or real type. Integer Numbers Number storage is defined as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal.
The representation has three tokens with an optional sign preceding it. Numbers may be sized or unsized. Unsized integers default to at least 32 bits. Logical Values: Operators They are of three types. The top of the table is the highest precedence, and the bottom is the lowest. Operators listed on the same line have the same precedence. All operators associate left to right in an expression. Parentheses can be used to change the precedence or clarify the situation.
Data Types Verilog has two major data type classes: Nets Net data types are used to make connections between parts of a design. Nets reflect the value and strength level of the drivers of the net or the capacitance of the net, and do not have a value of their own.
A net can be specified in different ways. Wire A wire or net represents a physical wire in a circuit and is used to connect gates or modules. The value of a wire can be read, but not assigned to, in a function or block. A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output of a gate or module. Syntax wire [msb: Variables can only be assigned a value from within an initial procedure, an always procedure, a task or a function.
Variables can only store logic values; they cannot store logic strength. Variables are un- initialized at the start of simulation, and will contain logic X until a value is assigned. Variables can be declared trough a keyword reg.
Reg A reg register is a data object that holds its value from one procedural assignment to the next. They are used only in functions and procedural blocks. A reg is a Verilog variable type and does not necessarily imply a physical register. Syntax reg [msb: A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port list arguments.
The default port width is 1 bit. Then the port variables must be declared wire or reg. The default is wire.
Typically inputs are wire since their data is latched outside the module. Outputs are type reg if their signals were stored inside an always or initial block. It is the normal assignment outside of always or initial blocks. Continuous assignment is done with an assign statement or by assigning a value to a wire during its declaration.
The order of assign statements does not matter. A change in any of the right-hand-side inputs will immediately reflect on the left-hand-side output. Behavioral Modeling Behavioral or procedural statements in Verilog are used to model a design at a higher level of abstraction than the other levels. Procedural assignments are used within Verilog procedures always and initial blocks. The assignment may be Blocking or non-Blocking. Expression is evaluated and assigned when the statement is encountered.
In a begin—end sequential statement group, execution of the next statement is blocked until the assignment is complete.
The first assignment changes m before the second assignment reads m. Expression is evaluated when the statement is encountered, and assignment is postponed until the end of the simulation time-step.
In a begin—end sequential statement group, execution of the next statement is not blocked; and will be evaluated before the assignment is complete. Both assignments will be evaluated before m or n changes. Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation. This also means that all always blocks in a module execute simultaneously.
The always block is triggered to execute by the level, positive edge or negative edge of one or more signals separate signals by the keyword or. A double-edge trigger is implied if you include a signal in the event list of the always statement. The single edge-triggers are specified by posedge and negedge keywords.
It is typically used to initialize variables and specify signal waveforms during simulation. Initial blocks are not supported for synthesis. This window allows the user create a New Project. It will have the following fields: